LSI 53C810A Manuel d'utilisateur

®S14067LSI53C810APCI to SCSI I/OProcessorTECHNICALMANUALMarch 2001Version 2.1

x ContentsFigures1.1 LSI53C810A System Diagram 1-71.2 LSI53C810A Chip Block Diagram 1-82.1 DMA FIFO Sections 2-82.2 LSI53C810A Host Interface Data Pat

5-26 Operating RegistersRegisters:0x10–0x13 (0x90–0x93)Data Structure Address (DSA)Read/WriteDSA Data Structure Address [31:0]This 32-bit register con

5-273. Read the Interrupt Status (ISTAT) register.4. If the SCSI Interrupt Pending bit is set, then read theSCSI Interrupt Status Zero (SIST0) or SCSI

5-28 Operating Registersalso notify the LSI53C810A of a predefined condition andthe SCRIPTS processor may take action while SCRIPTSare executing.CON Co

5-29• A SCSI gross error occurs• An unexpected disconnect occurs• A SCSI reset occurs• A parity error is detected• The handshake-to-handshake timer is

5-30 Operating RegistersRegister: 0x19 (0x99)Chip Test One (CTEST1)Read OnlyFMT[3:0] Byte Empty in DMA FIFO [7:4]These bits identify the bottom bytes

5-31SIGP Signal Process 6This bit is a copy of the SIGP bit in the Interrupt Status(ISTAT) register (bit 5). The SIGP bit is used to signal arunning S

5-32 Operating RegistersRegister: 0x1B (0x9B)Chip Test Three (CTEST3)Read/WriteV[3:0] Chip Revision Level [7:4]These bits identify the chip revision l

5-33WRIE Write and Invalidate Enable 0This bit, when set, causes issuing of Memory Write andInvalidate commands on the PCI bus whenever legal.These co

5-34 Operating Registerswhen an interrupt occurs. These bits are unstable whiledata is being transferred between the two cores; once thechip has stopp

5-35ZMOD High Impedance Mode 6Setting this bit causes the LSI53C810A to place all outputand bidirectional pins into a high impedance state. Inorder to

Contents xi7.21 Target Asynchronous Send 7-297.22 Target Asynchronous Receive 7-307.23 Initiator and Target Synchronous Transfers 7-307.24 100 LD PQFP

5-36 Operating RegistersFBL[2:0] FIFO Byte Control [2:0]These bits steer the contents of the Chip Test Six(CTEST6) register to the appropriate byte la

5-37contents and the current DNAD value. This bitautomatically clears itself after decrementing the DMAByte Counter (DBC) register.R Reserved 5MASR Ma

5-38 Operating RegistersChip Test Four (CTEST4) register. Writes to this registerwhile the test mode is not enabled produces unexpectedresults.Registe

5-39Register: 0x27 (0xA7)DMA Command (DCMD)Read/WriteDCMD DMA Command [7:0]This 8-bit register determines the instruction for theLSI53C810A to execute

5-40 Operating Registersthe first SCRIPTS instruction is written to this register,SCRIPTS instructions are automatically fetched andexecuted until an i

5-41Registers:0x34–0x37 (0xB4–0xB7)Scratch Register A (SCRATCHA)Read/WriteSCRATCHA Scratch Register A [31:0]This is a general purpose, user-definable s

5-42 Operating RegistersSIOM Source I/O Memory Enable 5This bit is defined as an I/O Memory Enable bit for thesource address of a Memory Move or Block

5-43ERMP Enable Read Multiple 2Setting this bit causes Read Multiple commands to beissued on the PCI bus after certain conditions have beenmet. These

5-44 Operating RegistersRegister: 0x39 (0xB9)DMA Interrupt Enable (DIEN)Read/WriteThis register contains the interrupt mask bits corresponding to thei

5-45Register: 0x3A (0xBA)Scratch Byte Register (SBR)Read/WriteSBR Scratch Byte Register [7:0]This is a general purpose register. Apart from CPUaccess,

xii Contents7.10 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/,IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR/ 7-57.11 Bidirectional Signals—GPIO0_FETC

5-46 Operating RegistersSSM Single Step Mode 4Setting this bit causes the LSI53C810A to stop afterexecuting each SCRIPTS instruction, and generate asi

5-47assert. As with any register other than Interrupt Status(ISTAT), this register cannot be accessed except by aSCRIPTS instruction during SCRIPTS ex

5-48 Operating RegistersRegister: 0x40 (0xC0)SCSI Interrupt Enable Zero (SIEN0)Read/WriteThis register contains the interrupt mask bits that correspon

5-49• Data underflow – reading the SCSI FIFO when nodata was present.• Data overflow – writing to the SCSI FIFO while it isfull.• Offset underflow – rece

5-50 Operating RegistersRegister: 0x41 (0xC1)SCSI Interrupt Enable One (SIEN1)Read/WriteThis register contains the interrupt mask bits corresponding t

5-51Register: 0x42 (0xC2)SCSI Interrupt Status Zero (SIST0)Read OnlyReading the SCSI Interrupt Status Zero (SIST0) register returns thestatus of the v

5-52 Operating RegistersSEL Selected 5This bit is set when the LSI53C810A is selected byanother SCSI device. The Enable Response to Selectionbit must

5-53when the LSI53C810A operates in the initiator mode.When the LSI53C810A operates in low level mode, anydisconnect causes an interrupt, even a valid

5-54 Operating RegistersR Reserved [7:3]STO Selection or Reselection Time-out 2When the SCSI device which the LSI53C810A isattempting to select or res

5-55A one in any bit position of the final SCSI LongitudinalParity (SLPAR) value would indicate a transmission error.The SCSI Longitudinal Parity (SLPA

LSI53C810A PCI to SCSI I/O Processor 1-1Chapter 1General DescriptionChapter 1 is divided into the following sections:• Section 1.1, “TolerANT®Technolo

5-56 Operating RegistersWhen bits 3 through 0 are set, the corresponding accessis considered local and the MAC/_TESTOUT pin is drivenhigh. When these

5-57FE Fetch Enable 6The internal opcode fetch signal is presented on GPIO0if this bit is set, regardless of the state of bit 0(GPIO0_EN).R Reserved 5

5-58 Operating RegistersSEL Selection Time-Out [3:0]These bits select the SCSI selection/reselection time-outperiod. When this timing (plus the 200 µs

5-59GEN bit in the SCSI Interrupt Status One (SIST1) registeris set. Refer to the table under SCSI Timer Zero(STIME0), bits [3:0], for the available t

5-60 Operating RegistersRegister: 0x4C (0xCC)SCSI Test Zero (STEST0)Read OnlyR Reserved 7SSAID SCSI Selected As ID [6:4]These bits contain the encoded

5-61SOM SCSI Synchronous Offset Maximum 0This bit indicates that the current synchronousSREQ/SACK offset is the maximum specified by bits [3:0]in the S

5-62 Operating RegistersRegister: 0x4E (0xCE)SCSI Test Two (STEST2)Read/WriteSCE SCSI Control Enable 7Setting this bit allows assertion of all SCSI co

5-63R Reserved 2EXT Extend SREQ/SACK Filtering 1LSI Logic TolerANT SCSI receiver technology includes aspecial digital filter on the SREQ/ and SACK/ pin

5-64 Operating RegistersLSI53C810A is in an information transfer phase.TolerANT active negation should be enabled to improvesetup and deassertion time

5-65SCSI Input Data Latch (SIDL), SCSI Output Data Latch(SODL), and SODR full bits in the SCSI Status Zero(SSTAT0) register are cleared.STW SCSI FIFO

1-2 General DescriptionSoftware development tools are available to developers who use theSCSI SCRIPTS language to create customized SCSI softwareappli

5-66 Operating RegistersRegisters:0x54 (0xD4)SCSI Output Data Latch (SODL)Read/WriteSODL SCSI Output Data Latch [15:0]This register is used primarily

LSI53C810A PCI to SCSI I/O Processor 6-1Chapter 6Instruction Set of theI/O ProcessorThis chapter is divided into the following sections:• Section 6.1,

6-2 Instruction Set of the I/O Processor6.2 SCSI SCRIPTSTo operate in the SCSI SCRIPTS mode, the LSI53C810A requires onlya SCRIPTS start address. The

SCSI SCRIPTS 6-3Each instruction consists of two or three 32-bit words. The first 32-bitword is always loaded into the DMA Command (DCMD) and DMA ByteC

6-4 Instruction Set of the I/O Processor• The LSI53C810A typically fetches two Dwords (64 bits) and decodesthe high order byte of the first Dword as a

Block Move Instructions 6-5Figure 6.1 SCRIPTS Overview6.3 Block Move InstructionsThe Block Move SCRIPTS instruction is used to move data between theSC

6-6 Instruction Set of the I/O Processor6.3.1 First DwordIT[1:0] Instruction Type - Block Move [31:30]IA Indirect Addressing 29When this bit is cleare

Block Move Instructions 6-7Note: Do not use indirect and table indirect addressingsimultaneously; use only one addressing method at a time.TIA Table I

6-8 Instruction Set of the I/O ProcessorFigure 6.2 Block Move Instruction RegisterPrior to the start of an I/O, the Data Structure Address(DSA) regist

Block Move Instructions 6-9SCRIPTS can directly execute operating system I/O datastructures, saving time at the beginning of an I/Ooperation. The I/O

LSI53C810A Benefits Summary 1-31.2 LSI53C810A Benefits SummaryThis section provides an overview of the LSI53C810A features andbenefits. It contains these

6-10 Instruction Set of the I/O Processor– If any other Group Code is received, the DMA ByteCounter (DBC) register is not modified and theLSI53C810A wi

Block Move Instructions 6-113. The LSI53C810A compares the SCSI phase bits inthe DMA Command (DCMD) register with the latchedSCSI phase lines stored i

6-12 Instruction Set of the I/O ProcessorTC[23:0] Transfer Counter [23:0]This 24-bit field specifies the number of data bytes to bemoved between the LSI

I/O Instruction 6-13indirect addressing, the value in this field is an offset intoa table pointed to by the Data Structure Address (DSA).The table entr

6-14 Instruction Set of the I/O ProcessorReselect Instruction1. The LSI53C810A arbitrates for the SCSI bus byasserting the SCSI ID stored in the SCSI

I/O Instruction 6-15Wait Select Instruction1. If the LSI53C810A is selected, it fetches the nextinstruction from the address pointed to by the DMASCRI

6-16 Instruction Set of the I/O ProcessorFigure 6.3 illustrates the register bit values that represent an I/Oinstruction.Figure 6.3 I/O Instruction Re

I/O Instruction 6-17Clear InstructionWhen the SACK/ or SATN/ bits are cleared, thecorresponding bits are cleared in the SCSI Output Con-trol Latch (SO

6-18 Instruction Set of the I/O Processorfield stored in the DMA Next Address (DNAD) register.Manually set the LSI53C810A to Initiator mode if it isres

I/O Instruction 6-19Clear InstructionWhen the SACK/or SATN/ bits are cleared, thecorresponding bits are cleared in the SCSI Output Con-trol Latch (SOC

1-4 General Description1.2.2 PCI PerformanceTo improve PCI performance, the LSI53C810A:• Bursts 2, 4, 8, or 16 Dwords across PCI bus with 80-byte DMA

6-20 Instruction Set of the I/O Processor• An I/O command structure must have all four bytescontiguous in system memory, as shown below. Theoffset/per

I/O Instruction 6-21Table RelativeTreats the alternate jump address as a relative jump andfetches the device ID, synchronous offset, andsynchronous pe

6-22 Instruction Set of the I/O ProcessorACK Set/Clear SACK/ 6ATN Set/Clear SATN/ 3These two bits are used in conjunction with a Set or Clearinstructi

Read/Write Instructions 6-236.5 Read/Write InstructionsThe Read/Write instruction type moves the contents of one register toanother, or performs arith

6-24 Instruction Set of the I/O ProcessorThe Add operation is used to increment or decrement register values (ormemory values if used in conjunction w

Read/Write Instructions 6-25Figure 6.4 illustrates the register bit values that represent a Read/Writeinstruction.Figure 6.4 Read/Write Register Instr

6-26 Instruction Set of the I/O ProcessorTable 6.2 Read/Write InstructionsOperatorOpcode 111Read-Modify-WriteOpcode 110Move to SFBROpcode 101Move from

Transfer Control Instructions 6-27Miscellaneous Notes:˘ Substitute the desired register name or address for “RegA” in the syntax examples.˘ data8 indi

6-28 Instruction Set of the I/O ProcessorJump InstructionThe LSI53C810A can do a true/false comparison of theALU carry bit, or compare the phase and/o

Transfer Control Instructions 6-29If the comparisons are false, the LSI53C810A fetches thenext instruction from the address pointed to by the DMASCRIP

LSI53C810A Benefits Summary 1-5• Three programmable SCSI timers: Select/Reselect, Handshake-to-Handshake, and General Purpose. The time-out period ispr

6-30 Instruction Set of the I/O ProcessorFigure 6.5 illustrates the register bit values that represent a TransferControl instruction.Figure 6.5 Transf

Transfer Control Instructions 6-31If the comparisons are false, the LSI53C810A fetches thenext instruction from the address pointed to by the DMASCRIP

6-32 Instruction Set of the I/O ProcessorRA Relative Addressing Mode 23When this bit is set, the 24-bit signed value in the DMASCRIPTS Pointer Save (D

Transfer Control Instructions 6-33A relative transfer can be to any address within a16 Mbyte segment. The program counter is combinedwith the 24-bit s

6-34 Instruction Set of the I/O ProcessorCD Compare Data 18When this bit is set, the first byte received from the SCSIdata bus (contained in SCSI First

Transfer Control Instructions 6-356.6.2 Second DwordJump Address [31:0]This 32-bit field contains the address of the nextinstruction to fetch when a ju

6-36 Instruction Set of the I/O Processor6.7 Memory Move InstructionsThis SCRIPTS instruction allows the LSI53C810A to executehigh-performance block m

Memory Move Instructions 6-37Figure 6.6 illustrates the register bit values that represent a MemoryMove instruction.Figure 6.6 Memory to Memory Move I

6-38 Instruction Set of the I/O ProcessorThe DMA SCRIPTS Pointer Save (DSPS) and Data Structure Address(DSA) registers are additional holding register

Load and Store Instructions 6-396.7.4 Read/Write System Memory from a SCRIPTS InstructionBy using the Memory Move instruction, single or multiple regi

1-6 General Description• Controlled bus assertion times (reduces RFI, improves reliability, andeases FCC certification)• Latch-up protection greater th

6-40 Instruction Set of the I/O Processoroperating register set of the chip. If it does, a PCI illegal read/write cycleoccur, the chip issues an inter

Load and Store Instructions 6-41Note: This bit has no effect unless the Prefetch Enable bit in theDMA Control (DCNTL) register is set. For information

6-42 Instruction Set of the I/O ProcessorFigure 6.7 illustrates the register bit values that represent a Load andStore instruction.Figure 6.7 Load and

LSI53C810A PCI to SCSI I/O Processor 7-1Chapter 7ElectricalCharacteristicsThis chapter specifies the LSI53C810A electrical and mechanicalcharacteristic

7-2 Electrical CharacteristicsTable 7.1 Absolute Maximum Stress RatingsSymbol Parameter Min Max Unit Test ConditionsTSTGStorage temperature −55 150 °C

DC Characteristics 7-3Table 7.3 SCSI Signals—SD[7:0]/, SDP/, SREQ/, SACK/Symbol Parameter Min Max Unit Test ConditionsVIHInput high voltage 2.0 VDD+0.

7-4 Electrical CharacteristicsTable 7.6 CapacitanceSymbol Parameter Min Max Unit Test ConditionsCIInput capacitance of input pads – 7 pF –CIOInput cap

DC Characteristics 7-5Table 7.9 Output Signal—SERR/Symbol Parameter Min Max Unit Test ConditionsVOLOutput low voltage VSS0.4 V 16 mAIOLOutput low curr

7-6 Electrical Characteristics7.2 TolerANT TechnologyThe LSI53C810A features TolerANT technology, which includes activenegation on the SCSI drivers an

TolerANT Technology 7-7Table 7.12 TolerANT Technology Electrical CharacteristicsSymbol Parameter Min Max Unit Test ConditionsVOH11. Active negation ou

LSI53C810A Benefits Summary 1-7Figure 1.1 LSI53C810A System DiagramPCI Bus LSI53C810A40 MHz Oscillator orSCSI BusPeripheralBulkheadCPU BoxCPU Baseboard

7-8 Electrical CharacteristicsFigure 7.1 Rise and Fall Time Test ConditionsFigure 7.2 SCSI Input FilteringFigure 7.3 Hysteresis of SCSI Receiver2.5 V4

TolerANT Technology 7-9Figure 7.4 Input Current as a Function of Input VoltageFigure 7.5 Output Current as a Function of Output Voltage+40+200−20−40−4

7-10 Electrical Characteristics7.3 AC CharacteristicsThe AC characteristics described in this section apply over the entirerange of operating conditio

AC Characteristics 7-11Table 7.14 and Figure 7.7 provide reset input timing data.Figure 7.7 Reset InputTable 7.15 and Figure 7.8 provide interrupt out

7-12 Electrical Characteristics7.4 PCI Interface Timing DiagramsFigure 7.9 through Figure 7.18 represent signal activity when theLSI53C810A accesses t

PCI Interface Timing Diagrams 7-137.4.1 Target TimingFigure 7.9 through Figure 7.12 describe target timing.Figure 7.9 PCI Configuration Register ReadDa

7-14 Electrical CharacteristicsFigure 7.10 PCI Configuration Register Writet1t2CLK(Driven by System)FRAME/(Driven by Master)Addr InData InByte Enablet2

PCI Interface Timing Diagrams 7-15Figure 7.11 Target ReadDataByte Enablet2t1t2t1t2t1t1t2t2t3t2t1t3CLK(Driven by System)FRAME/(Driven by Master)AD/(Dri

7-16 Electrical CharacteristicsFigure 7.12 Target WriteByte EnableCMDt2t1t2t1t2t1t1t2t2t3t2t1t3CLK(Driven by System)FRAME/(Driven by Master)AD/(Driven

PCI Interface Timing Diagrams 7-177.4.2 Initiator TimingFigure 7.13 through Figure 7.18 describe initiator timing.Figure 7.13 OpCode Fetch, NonburstCL

iiThis document contains proprietary information of LSI Logic Corporation. Theinformation contained herein is not to be used by or disclosed to third

1-8 General DescriptionFigure 1.2 LSI53C810A Chip Block DiagramPCI Master and Slave Control BlockDataFIFO80 BytesSCSISCRIPTSOperatingRegistersConfigura

7-18 Electrical CharacteristicsFigure 7.14 Burst Opcode FetchCLK(Driven by System)FRAME/(Driven by LSI53C810A)AD/(Driven by LSI53C810A-C_BE/(Driven by

PCI Interface Timing Diagrams 7-19Figure 7.15 Back-to-Back ReadCLK(Driven by System)FRAME/(Driven by LSI53C810A)AD/(Driven by LSI53C810A-C_BE/(Driven

7-20 Electrical CharacteristicsFigure 7.16 Back-to-Back WriteCLK(Driven by System)FRAME/(Driven by LSI53C810A)AD/(Driven by LSI53C810A)C_BE/(Driven by

PCI Interface Timing Diagrams 7-21This page intentionally left blank.

7-22 Electrical CharacteristicsFigure 7.17 Burst Readt1t2CLKGPIO0_FETCH/(Driven by LSI53C810A)GPIO1_MASTER/(Driven by LSI53C810A)REQ/(Driven by LSI53C

PCI Interface Timing Diagrams 7-23Figure 7.17 Burst Read (Cont.)t1CMDt2BEData InOutIn InOutInBEAddrOutCLKGPIO0_FETCH/(Driven by LSI53C810A)GPIO1_MASTE

7-24 Electrical CharacteristicsFigure 7.18 Burst WriteCLK(Driven by System)GPIO0_FETCH/PAR(Driven by LSI53C810A)IRDY/(Driven by LSI53C810A)TRDY/(Drive

PCI Interface Timing Diagrams 7-25Figure 7.18 Burst Write (Cont.)t1t2AddrOutBEDataOutCMDt1t2BEDataOutDataOutCLK(Driven by System)GPIO0_FETCH/PAR(Drive

7-26 Electrical Characteristics7.5 PCI Interface TimingTable 7.16 describes the PCI timing data for the LSI53C810A.Table 7.16 PCI TimingSymbol Paramet

SCSI Timings 7-277.6 SCSI TimingsTables 7.17 through 7.23 and Figures 7.19 through 7.23 describe theLSI53C810A SCSI timing data.Figure 7.19 Initiator

LSI53C810A PCI to SCSI I/O Processor 2-1Chapter 2Functional DescriptionChapter 2 is divided into the following sections:• Section 2.1, “SCSI Core”• Se

7-28 Electrical CharacteristicsFigure 7.20 Initiator Asynchronous ReceiveTable 7.18 Initiator Asynchronous Receive (5 Mbytes/s)Symbol Parameter Min Ma

SCSI Timings 7-29Figure 7.21 Target Asynchronous SendTable 7.19 Target Asynchronous Send (5 Mbytes/s)Symbol Parameter Min Max Unitt1SACK/ asserted fro

7-30 Electrical CharacteristicsFigure 7.22 Target Asynchronous ReceiveFigure 7.23 Initiator and Target Synchronous TransfersTable 7.20 Target Asynchro

SCSI Timings 7-31Table 7.21 SCSI-1 Transfers (SE, 5.0 Mbytes/s)Symbol Parameter Min Max Unitt1Send SREQ/ or SACK/ assertion pulse width 90 – nst2Send

7-32 Electrical CharacteristicsTable 7.23 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers), 50 MHz Clock)Symbol Parameter Min Max Unitt1Send SRE

Package Drawings 7-337.7 Package DrawingsFigure 7.24 illustrates the mechanical drawing for the LSI53C810A.

7-34 Electrical CharacteristicsFigure 7.24 100 LD PQFP (UD) Mechanical Drawing (Sheet 1 of 2)Important: This drawing may not be the latest version. Fo

Package Drawings 7-35Figure 7.24 100 LD PQFP (UD) Mechanical Drawing (Sheet 2 of 2)Important: This drawing may not be the latest version. For board la

7-36 Electrical Characteristics

LSI53C810A PCI to SCSI I/O Processor A-1Appendix ARegister SummaryTable A.1 lists the LSI53C810A configuration registers by register name.Table A.1 Con

2-2 Functional Descriptionand diagnostic procedures. In support of loopback diagnostics, the SCSIcore can perform a self-selection and operate as both

A-2 Register SummaryTable A.2 lists the LSI53C810A SCSI registers by register name.Table A.2 SCSI RegistersRegister Name Address Read/Write PageAdder

Register Summary A-3Scratch Byte Register (SBR) 0x3A (0xBA) Read/Write 5-45Scratch Register A (SCRATCHA) 0x34–0x37 (0xB4–0xB7) Read/Write 5-41SCSI Bus

A-4 Register SummarySCSI Test Two (STEST2) 0x4E (0xCE) Read/Write 5-62SCSI Test Zero (STEST0) 0x4C (0xCC) Read Only 5-60SCSI Timer One (STIME1) 0x49 (

LSI53C810A PCI to SCSI I/O Processor IX-1IndexSymbols(AD[31:0]) 4-6(BARO[31:0]) 3-17(BARZ[31:0]) 3-17(CLS[7:0]) 3-16(FMT) 5-29(HT[7:0]) 3-17(IL[7:0])

IX-2 Indexclock address incrementor bit 5-36clock byte counter bit 5-36clock conversion factor bits 5-10CLSE bit 5-45CM bit 5-31CMP bit 5-48, 5-51COM

Index IX-3II/O bit 5-25I/O instructions 6-13I_O bit 5-18IARB bit 5-7IDSEL 4-7IID bit 5-22, 5-44illegal instruction detected bit 5-22, 5-44immediate ar

IX-4 IndexSCSI bus data lines 5-66SCSI chip ID 5-11SCSI control one register 5-6SCSI control register two 5-9SCSI control three 5-9SCSI control zero 5

Index IX-50x41 5-500x42 5-510x43 5-530x44 5-540x46 5-550x47 5-560x48 5-570x49 5-580x4A 5-590x4C 5-600x4D 5-610x4E 5-620x4F 5-630x50 5-650x54 5-660x58

IX-6 IndexSCRIPTS interrupt instruction received 5-21, 5-44SCSI C_D/ signal 5-25SCSI control enable 5-62SCSI data high impedance 5-35SCSI disconnect u

Index IX-7SCSI I_O/ bit 5-25SCSI input data latch register 5-65SCSI instructionsblock move 6-5I/O 6-13load/store 6-39memory move 6-36read/write 6-23SC

Prefetching SCRIPTS Instructions 2-3A complete set of development tools is available for writing customdrivers with SCSI SCRIPTS. For more information

IX-8 IndexStorage Device Management System (SDMS) 2-3STR bit 5-64STW bit 5-65SXFER register 5-12synchronous clock conversion factor bits 5-9synchronou

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2-4 Functional Descriptionthe prefetch unit contents, use the No Flush Memory to MemoryMove (NFMMOV) instruction for all MMOV operations that do notmo

Parity Options 2-5Write and Invalidate are each software enabled or disabled to allow theuser full flexibility in using these commands. For more inform

2-6 Functional DescriptionTable 2.1 Bits Used for Parity Control and ObservationBIt Name Location DescriptionAssert SATN/ on ParityErrorsSCSI ControlZ

Parity Options 2-7Table 2.2 SCSI Parity ControlEPC AESP Description0 0 Does not check for parity errors. Parity is generated when sendingSCSI data. As

2-8 Functional Description2.5.1 DMA FIFOThe DMA FIFO is divided into four sections, each one byte wide and20 transfers deep. The DMA FIFO is illustrat

Parity Options 2-9Asynchronous SCSI Send –Step 1. Look at the DMA FIFO (DFIFO) and DMA Byte Counter (DBC)registers and calculate if there are bytes le

Preface iiiPrefaceThis book is the primary reference and technical manual for the LSI LogicLSI53C810A PCI to SCSI I/O Processor. It contains a complet

2-10 Functional DescriptionStep 2. Read bit 7 in the SCSI Status Zero (SSTAT0) register todetermine if any bytes are left in the SCSI Input Data Latch

SCSI Bus Interface 2-112.6 SCSI Bus InterfaceThe LSI53C810A supports SE operation only. All SCSI signals are activeLOW. The LSI53C810A contains the SE

2-12 Functional DescriptionOnce a change in operating mode occurs, the initiator SCRIPTS shouldstart with a Set Initiator instruction or the target SC

SCSI Bus Interface 2-132.6.3 Synchronous OperationThe LSI53C810A can transfer synchronous SCSI data in both theinitiator and target modes. The SCSI Tr

2-14 Functional Description2.6.3.3 SCNTL3 Register, Bits [2:0] (CCF[2:0])The CCF[2:0] bits select the frequency of the SCLK for asynchronousSCSI opera

Interrupt Handling 2-15Figure 2.4 Determining the Synchronous Transfer Rate2.7 Interrupt HandlingThe SCRIPTS processor in the LSI53C810A performs most

2-16 Functional Descriptionthat could be used for other system tasks. The preferred method ofdetecting interrupts in most systems is hardware interrup

Interrupt Handling 2-17If the LSI53C810A is sending data to the SCSI bus and a fatal SCSIinterrupt condition occurs, data could be left in the DMA FIF

2-18 Functional Description2.7.1.2 Fatal vs. Nonfatal InterruptsA fatal interrupt, as the name implies, always causes SCRIPTS to stoprunning. All nonf

Interrupt Handling 2-19whether polling or hardware interrupts are being used; whether theinterrupt is fatal or nonfatal; and whether the chip is opera

iv Preface• Chapter 6, Instruction Set of the I/O Processor, defines all of theSCSI SCRIPTS instructions that are supported by the LSI53C810A.• Chapter

2-20 Functional Descriptioninterrupts are cleared, all the interrupts that came in afterward move intoSIST0, SIST1, and DSTAT. After the first interrup

Interrupt Handling 2-21• If the DMA direction is a write to memory and a SCSI interruptoccurs, the LSI53C810A attempts to flush the DMA FIFO to memoryb

2-22 Functional Descriptionconsecutive reads to ensure that the interrupts clear properly. Boththe SCSI and DMA interrupt conditions should be handled

LSI53C810A PCI to SCSI I/O Processor 3-1Chapter 3PCI FunctionalDescriptionChapter 3 is divided into the following sections:• Section 3.1, “PCI Address

3-2 PCI Functional DescriptionThe LSI53C810A operating registers are available in both the upper andlower 128-byte portions of the 256-byte space sele

PCI Cache Mode 3-33.1.2.3 Memory Read CommandThe Memory Read reads data from an agent mapped in memoryaddress space. All 32 address bits are decoded.3

3-4 PCI Functional Description3.2.2 Selection of Cache Line SizeThe cache logic selects a cache line size based on the values for theburst size in the

PCI Cache Mode 3-53.2.3.2 Memory Write and Invalidate CommandThe Memory Write and Invalidate command is identical to the MemoryWrite command, except t

3-6 PCI Functional Descriptionfinish the transfer at a later time using another bus ownership. If the chipis transferring multiple cache lines it conti

PCI Cache Mode 3-7If cache mode is enabled, a Read Line command is issued on all readcycles, except opcode fetches, when the following conditions are

Preface vPCI Special Interest Group2575 N. E. KatherineHillsboro, OR 97214(800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344SCSI SCRIP

3-8 PCI Functional DescriptionWhen these conditions are met, the chip issues a Read Multiplecommand instead of a Memory Read during all PCI read cycle

Configuration Registers 3-93.3 Configuration RegistersThe Configuration registers are accessible only by system BIOS duringPCI configuration cycles, and a

3-10 PCI Functional DescriptionNote: The configuration register descriptions are provided forgeneral information only, to indicate which PCIconfiguratio

Configuration Registers 3-11Register: 0x00Vendor IDRead OnlyVID Vendor ID [15:0]This field identifies the manufacturer of the device. TheVendor ID is 0x1

3-12 PCI Functional DescriptionR Reserved [15:9]SE SERR/ Enable 8This bit enables the SERR/ driver. SERR/ is disabledwhen this bit is cleared. The def

Configuration Registers 3-13EIS Enable I/O Space 0This bit controls the LSI53C810A’s response to I/O spaceaccesses. A value of zero disables the respon

3-14 PCI Functional DescriptionRTA Received Target Abort (from Master) 12A master device should set this bit whenever itstransaction is terminated wit

Configuration Registers 3-15Register: 0x08Revision IDRead OnlyRID Revision ID [7:0]This register specifies device and revision identifiers. Inthe LSI53C8

3-16 PCI Functional DescriptionRegister: 0x0CCache Line SizeRead/WriteCLS Cache Line Size [7:0]This register specifies the system cache line size in un

Configuration Registers 3-17Register: 0x0EHeader TypeRead OnlyHT Header Type [7:0]This register identifies the layout of bytes 0x10 through0x3F in config

vi Preface

3-18 PCI Functional DescriptionRegister: 0x3CInterrupt LineRead/WriteIL Interrupt Line [7:0]This register is used to communicate interrupt line routin

Configuration Registers 3-19Register: 0x3EMin_GntRead OnlyMG Min_Gnt [7:0]This register is used to specify the desired settings forLatency Timer values

3-20 PCI Functional Description

LSI53C810A PCI to SCSI I/O Processor 4-1Chapter 4Signal DescriptionsThis chapter presents the LSI53C810A pin configuration and signaldefinitions using t

4-2 Signal DescriptionsFigure 4.1 LSI53C810A Pin DiagramA slash (/) at the end of the signal name indicates that the active stateoccurs when the signa

4-3Signals are assigned a type. There are four signal types:Table 4.1 describes the Power and Ground Signals group.I Input, a standard input only sign

4-4 Signal DescriptionsFigure 4.2 Functional Signal GroupingCLKRSTAD[31:0]C_BE/[3:0]PARFRAME/TRDY/IRDY/STOP/DEVSEL/IDSELREQ/GNT/SERR/PERR/GPIO0_FETCH/

PCI Bus Interface Signals 4-54.1 PCI Bus Interface SignalsThe PCI signal definitions are organized into the following functionalgroups: Power and Groun

4-6 Signal Descriptions4.1.2 Address and Data SignalsTable 4.3 describes the Address and Data Signals group.Table 4.3 Address and Data SignalsName Pin

PCI Bus Interface Signals 4-74.1.3 Interface Control SignalsTable 4.4 describes the Interface Control Signals group.Table 4.4 Interface Control Signal

Contents viiContentsChapter 1 General Description1.1 TolerANT®Technology 1-21.2 LSI53C810A Benefits Summary 1-31.2.1 SCSI Performance 1-31.2.2 PCI Perf

4-8 Signal Descriptions4.1.4 Arbitration SignalsTable 4.5 describes the Arbitration Signals group.4.1.5 Error Reporting SignalsTable 4.6 describes the

SCSI Bus Interface Signals 4-94.2 SCSI Bus Interface SignalsThe SCSI signal definitions are organized into the following functionalgroups: SCSI Bus Int

4-10 Signal Descriptions4.2.2 Additional Interface SignalsTable 4.8 describes the Additional Interface Signals group.Table 4.8 Additional Interface Si

SCSI Bus Interface Signals 4-11MAC/_TESTOUT53 T/S Memory Access Control. This pin can be programmed to indicatelocal or system memory accesses (non-PC

4-12 Signal Descriptions

LSI53C810A PCI to SCSI I/O Processor 5-1Chapter 5Operating RegistersThis chapter describes all LSI53C810A operating registers. Table 5.1, theregister

5-2 Operating RegistersFigure 5.1 Register Address MapRegister: 0x00 (0x80)SCSI Control Zero (SCNTL0)Read/Write31 16 15 0 Mem I/O ConfigSCNTL3 SCNTL2 S

5-3ARB[1:0] Arbitration Mode Bits 1 and 0 [7:6]Simple Arbitration1. The LSI53C810A waits for a bus free condition tooccur.2. It asserts SBSY/ and its

5-4 Operating Registers4. The LSI53C810A repeats arbitration until it winscontrol of the SCSI bus. When it wins, the WonArbitration bit is set in the

5-5EPC Enable Parity Checking 3When this bit is set, the SCSI data bus is checked for oddparity when data is received from the SCSI bus in eitherthe i

viii Contents2.7 Interrupt Handling 2-152.7.1 Polling and Hardware Interrupts 2-15Chapter 3 PCI Functional Description3.1 PCI Addressing 3-13.1.1 Confi

5-6 Operating RegistersRegister: 0x01 (0x81)SCSI Control One (SCNTL1)Read/WriteEXC Extra Clock Cycle of Data Setup 7When this bit is set, an extra clo

5-7When this bit is set, the LSI53C810A does not halt theSCSI transfer when SATN/ or a parity error is received.CON Connected 4This bit is automatical

5-8 Operating Registersbit is cleared automatically when the selection orreselection sequence is completed, or times out.Interrupts do not occur until

5-9Register: 0x02 (0x82)SCSI Control Two (SCNTL2)Read/WriteSDU SCSI Disconnect Unexpected 7This bit is valid in the initiator mode only. When this bit

5-10 Operating Registersdetermines the transfer rate. For example, if SCLK is40 MHz and the SCF value is set to divide by one, thenthe maximum synchro

5-11Register: 0x04 (0x84)SCSI Chip ID (SCID)Read/WriteR Reserved 7RRE Enable Response to Reselection 6When this bit is set, the LSI53C810A is enabled

5-12 Operating RegistersR Reserved [4:3]ENC[2:0] Encoded LSI53C810A Chip SCSI ID [2:0]These bits are used to store the LSI53C810A encodedSCSI ID. This

5-13Use the following formula to calculate the synchronoussend and receive rates. Table 5.3 and Table 5.4 showexamples of possible bit combinations.Sy

5-14 Operating RegistersR Reserved 4MO[3:0] Max SCSI Synchronous Offset [3:0]These bits describe the maximum SCSI synchronousoffset used by the LSI53C

5-15the LSI53C810A. These bits determine theLSI53C810A’s method of transfer for Data-In andData-Out phases only; all other information transfersoccur

Contents ix6.4.1 First Dword 6-136.4.2 Second Dword 6-226.5 Read/Write Instructions 6-236.5.1 First Dword 6-236.5.2 Second Dword 6-236.5.3 Read-Modify

5-16 Operating RegistersRegister: 0x07 (0x87)General Purpose (GPREG)Read/WriteR Reserved [7:2]GPIO[1:0] General Purpose [1:0]These bits are programmed

5-17Register: 0x08 (0x88)SCSI First Byte Received (SFBR)Read/WriteThis register contains the first byte received in any asynchronousinformation transfe

5-18 Operating RegistersRegister: 0x09 (0x89)SCSI Output Control Latch (SOCL)Read/WriteREQ Assert SCSI REQ/ Signal 7ACK Assert SCSI ACK/ Signal 6BSY A

5-19Register: 0x0A (0x8A)SCSI Selector ID (SSID)Read OnlyVAL SCSI Valid Bit 7If VAL is asserted, then the two SCSI IDs are detectedon the bus during a

5-20 Operating RegistersRegister: 0x0B (0x8B)SCSI Bus Control Lines (SBCL)Read OnlyREQ SREQ/ Status 7ACK SACK/ Status 6BSY SBSY/ Status 5SEL SSEL/ Sta

5-21in the Interrupt Status (ISTAT) register is also cleared. It is possible tomask DMA interrupt conditions individually through the DMA InterruptEna

5-22 Operating RegistersR Reserved 1IID Illegal Instruction Detected 0This status bit is set any time an illegal instruction isdetected, whether the L

5-23OLF SODL Full 5This bit is set when SCSI Output Data Latch (SODL)contains data. The SCSI Output Data Latch (SODL)register is the interface between

5-24 Operating RegistersRegister: 0x0E (0x8E)SCSI Status One (SSTAT1)Read OnlyFF[3:0] FIFO Flags [7:4]These four bits define the number of bytes that c

5-25MSG SCSI MSG/ Signal 2C/D SCSI C_D/ Signal 1I/O SCSI I_O/ Signal 0These three SCSI phase status bits (MSG, C/D, and I/O)are latched on the asserti